Architect Labs Says Its AI Took Redwood From Chip Spec to FPGA in Two Weeks

Architect Labs says its platform turned a written specification into a working FPGA implementation of its Redwood inference-chip architecture in under two weeks. The result points to a faster way to revise specialized AI hardware, but the company’s headline performance advantage depends on an unbuilt chip.

The faster loop

According to the company’s researchers, two human architects supplied a high-level specification, then the Architect Labs Platform handled performance modeling, hardware-description generation, testing, verification, firmware and kernel generation. Architect Labs says there was no human intervention below that specification.

The more consequential claim is not simply that an AI helped draft hardware, but that it can keep the design moving. After verified specification changes, Architect Labs says a revised design returned to the FPGA in less than 48 hours. The company contrasts that with conventional chip programs, where stages are commonly frozen as work proceeds and later changes may be deferred.

A measured prototype and a projected challenger

Redwood’s reported FPGA result is not yet a speed victory over Nvidia. In the company’s test on Qwen3 0.6B, Redwood Nano averaged 12.1 tokens per second at 250 MHz, versus 28 tokens per second for Nvidia’s Jetson Orin Nano at 1,020 MHz.

The Nvidia advantage reverses only in Architect Labs’ estimate for a Samsung 8nm-class implementation. The company projects 49 tokens per second, roughly half the Jetson baseline’s power draw, and a 3.4-times improvement in performance per watt. Those figures are modeled from FPGA results, not measurements from a fabricated Redwood chip.

Automation is not qualification

Architect Labs says every Redwood block reached 95% code and functional coverage without human verification engineers, and that testing found no bugs in the first RTL design sent from simulation to FPGA. It also says moving optimization runs onto the FPGA reduced their reported runtime from 15 hours to 15–30 minutes.

The decisive test is still ahead: physical design, tapeout and post-silicon validation. Architect Labs says it plans to scale Redwood to larger models and fabrics and is working toward a TSMC tapeout. If the design survives that path, the company argues that hardware teams could update chips around changing workloads instead of locking in assumptions years before deployment.