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Cognichip Launches Chip-Design AI Aimed at Predicting Physical Tradeoffs

ACI Enterprise spans design and verification, with named customers and an FPGA partner. Its predicted design gains still need a harder test.

By 2 min read
Cognichip Launches Chip-Design AI Aimed at Predicting Physical Tradeoffs
Cognichip Launches Chip-Design AI Aimed at Predicting Physical Tradeoffs

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Cognichip has launched ACI Enterprise, an AI system meant to predict how early chip-design decisions could affect the finished hardware—not just produce code. The idea is to help engineers compare choices before committing to a long run through their usual design tools. Cognichip says its models connect several stages of chip development, from written specifications and RTL, or the logic description, through circuits and physical layout. That lets the system estimate how a choice might affect power use, performance and chip area. It can also generate RTL and testbenches, track test coverage, investigate bugs and explore those tradeoffs. The distinction matters: these are predictions, not a replacement for verification. ACI can work alongside established electronic-design-automation tools, which still check the design. Cognichip says its models can explore options without running the conventional tool sequence for every proposed change. The value of that shortcut depends on how well the estimates match what the tools—and ultimately hardware—show. The company reports more than 40 customer engagements and has named Renesas and SiTime as customers for custom chip work. It has not disclosed measured time savings or evidence of prediction accuracy. Cognichip is also working with Altera to optimize ACI for its FPGA ecosystem, where developers can test designs on configurable chips. So the concrete signs of adoption are there, but the central question remains open: do ACI’s predicted gains hold up when designs face established verification and physical testing?

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3 key points

Cognichip’s ACI Enterprise is designed to help chip teams narrow design choices earlier by estimating how decisions across specifications, RTL, circuits, and layout may affect power, performance, and area. It works alongside existing electronic-design-automation tools rather than replacing their checks, and can generate testbenches and run FPGA-based tests. Cognichip reports more than 40 customer engagements and...

  1. 01

    ACI Enterprise can generate RTL and testbenches, track test coverage, investigate bugs, and explore power, performance, and area tradeoffs.

  2. 02

    Cognichip says its models can explore options without running a conventional EDA-tool sequence for every change; established tools still verify designs.

  3. 03

    The company reports more than 40 engagements, but does not disclose measured time savings or prediction performance.

Cognichip has launched ACI Enterprise with an ambitious pitch: AI that can anticipate how an early chip-design choice will affect the finished hardware. The company has named customers and described more than 40 engagements, but those figures measure activity, not whether its design predictions are accurate.

A model for consequences, not just code

Cognichip says its “physics-informed” models are trained across design levels, from specifications and RTL—a description of a chip’s logic—through circuits and physical layout. The aim is to assess how early choices may affect speed, power use and chip area later on. That is a different claim from simply generating design code.

Cognichip diagram connecting high-level chip design with physical design.
Cognichip illustrates its proposed link between design intent and physical consequences. The diagram describes the approach, not a performance test. Source: eejournal.com.

ACI Enterprise can work with a customer’s existing electronic design automation tools—the software engineers use to develop and check chips. It can call those tools when needed. Cognichip’s proposed advantage is that its models can explore possibilities without running a conventional tool sequence for every contemplated change. Whether the predictions hold up is the crucial test.

From requirements to a device you can test

The proposed workflow starts with requirements or an existing design that needs revising. ACI can generate RTL and testbenches, then create and run environments that check whether the design behaves as intended. It can track test coverage, identify bugs, investigate their causes and explore tradeoffs among power use, performance and chip area.

The system also supports FPGAs, chips developers can configure after manufacture. Chief product officer Stelios Diamantidis told EE Journal that users could start with written requirements or a whiteboard sketch. He said ACI can select and connect components and custom logic, then program an attached FPGA board for testing. Cognichip is working with Altera to optimize the system for its FPGA ecosystem.

Customers are engaged; results are the harder test

Diamantidis said Cognichip was involved in more than 40 customer engagements, most of them not publicly identified. The company has permission to name Renesas and SiTime as customers for custom chip designs. An engagement shows a team is working with Cognichip; it does not establish how much time ACI saved or how well its design choices performed.

Sources

  1. eejournal.comMove Over, HAL. New AI Thinks Like a Chip Designer

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