Harmonic adds software and chip-design verification to its Aristotle AI model

Harmonic said on October 27, 2026, that Aristotle can now verify software written in C and chip designs written in Verilog. The announcement takes its reasoning-focused AI model beyond mathematical proofs into engineering checks. It follows applications ranging from finding critical software bugs to rebuilding part of a fusion lab’s reactor-control software.

Mathematical reasoning moves into engineering

Harmonic was co-founded by Robinhood CEO Vlad Tenev. The startup describes its work as developing “mathematical superintelligence,” with reasoning at the center of its effort to reduce hallucinations and factual errors. That is the technical ambition behind Aristotle: using mathematical reasoning to address mistakes in AI output, now with software and chip designs added to its remit.

Aristotle is available with usage-based pricing, according to Reuters. The commercial offering accompanies a capability expansion covering two engineering targets: software code and chip designs.

Bug discoveries and verification are different tests

Researchers recently used Harmonic’s technology to uncover critical bugs in PHP, Reuters reported. The discoveries prompted a global rush to patch the vulnerabilities. Reuters placed the new capability announcement against increased scrutiny of AI’s growing use in detecting software flaws, giving the expansion a security context as well as an engineering one.

Those applications concern different tasks: discovering vulnerabilities and reconstructing software, rather than measuring verification accuracy. Neither example establishes the reliability of the newly announced capabilities. Support for checking C software and Verilog designs remains Harmonic’s capability claim, without an independent reliability measurement in the announcement.