IBM Research opens AI hardware course comparing five accelerator architectures

IBM Research has opened enrollment for a six-course Coursera specialization that follows the same AI model across five accelerator architectures. Announced October 19, Dataflow Architectures for AI: From Principles to Practice teaches engineers to examine how compilation, memory and scheduling affect execution—not just whether their PyTorch code runs. Its core labs use Google Colab rather than requiring specialized hardware.

Same model, different work beneath the code

The program compares GPUs, Google TPUs, the Cerebras Wafer-Scale Engine, the Groq Language Processing Unit and IBM Spyre. The starting point is the same PyTorch model definition. A compiler—the software that translates that definition for a particular chip—then produces different execution patterns, with different supported operations, data layouts and transformations.

GPUs distribute work across many parallel threads, using hardware-managed caches and specialized matrix units. TPUs use arrays of processing elements, with the XLA compiler directing how work is divided and data moves. Cerebras spreads computation and on-chip memory across a full wafer, while Groq relies on its compiler to schedule operations and data movement.

Spyre turns the model into a dataflow graph, a representation of operations and their connections. Its compiler chooses data layout and placement in software-managed memory; its runtime coordinates transfers and launches. Spyre is the main worked example because instructor Kaoutar El Maghraoui’s team works with it directly. IBM says general architectural principles come before system-specific examples.

GPUs prioritize flexibility and broad programmability. Other systems give up some of that flexibility in order to gain efficiency, determinism, scale, or tighter control over execution.

Kaoutar El Maghraoui, principal research scientist at IBM Research and course instructor

Finding the slowdown—or the wrong answer

The six courses move from the accelerator landscape through execution models, compilation, memory systems, debugging and performance optimization. One recurring lesson is that reducing arithmetic is not the only route to speed. For matrix multiplication and attention, data layout, synchronization and movement between memory levels can determine achievable performance.

Combining operations can remove intermediate memory traffic, but the benefit depends on what the compiler already keeps on chip. A tensor shape that fits one target cleanly may need padding or rearrangement on another. These differences explain why an optimization cannot simply be assumed to carry over between architectures.

The debugging lessons use an eight-layer classification of failures and teach students to compare intermediate outputs against a CPU or GPU reference. IBM illustrates the method with a torch-spyre bug: copying a 65-element tensor produced a wrong final value because the compiled copy covered only 64 elements, despite a correct transfer log.

Performance work separates computation time from transfer time, then attributes remaining costs to memory movement. Students build Roofline charts, which compare an operation’s measured performance with its expected limits. The course also treats scheduling as a possible bottleneck alongside computation and memory.

Colab for everyone, Spyre for partnered programs

Each course ends with a lab lasting about 90 minutes to two hours, with students writing and running their own code. The core labs use standard PyTorch in Google Colab and require no proprietary tools. Assignments include:

• Building a benchmarking tool and explaining the CPU-to-GPU performance gap.
• Tracing a transformer block and comparing ordinary execution with torch.compile.
• Reading a memory timeline during language-model inference and diagnosing three planted bugs.

The optional Dataflow Deep Dive gives students in partnered programs access to Spyre hardware. They inspect compiler-generated graphs, examine memory placement and measure traffic with hardware counters. That track is not required to complete the specialization or earn its professional certificate in AI Systems Performance Engineering.

This is not introductory AI training. IBM targets intermediate-to-advanced learners, including compiler engineers, hardware architects, graduate students and practitioners optimizing models across hardware. Prerequisites include intermediate Python and C/C++, familiarity with convolutional and transformer models, and basic computer architecture.