Qualcomm says its near-memory AI silicon passed a key lab test

Qualcomm’s bid to speed up AI by moving calculations closer to memory now has working silicon behind it. The company says lab tests validated its first-generation high-bandwidth computing design’s memory read-write path and near-memory calculations. That is a development milestone, not a product rollout: the Dragonfly AI250 platform that will use it is expected to begin sampling in early 2027.

The validation follows Qualcomm’s introduction of the architecture in July. As The Next Platform reported on November 2, engineers used industry-standard automated test equipment to validate the complete memory path and near-memory computations at production levels. The new disclosure moves the story beyond an architectural pitch to a tested implementation of the functions Qualcomm says make the design distinctive.

Qualcomm is targeting the “memory wall”: the point where feeding data to a processor limits AI performance more than the processor’s ability to calculate. For inference—the work of running a model to produce responses—the company argues that moving data is a central performance and energy problem. Its proposed answer changes where much of the calculation happens.

An accelerator underneath the memory

Rather than only provide faster memory to a separate processor, HBC puts a full AI accelerator beneath a stack of low-power memory known as LPDDR. Qualcomm says most AI processing in its first implementation stays within that package. Some operations can move to the central AI250 system-on-chip, depending on how the system is designed and implemented.

Gerardo Giaretta, Qualcomm’s vice president and general manager of datacenter CPU and AI, described the physical advantage to journalists and analysts. Data travels micrometers between the memory and compute rather than millimeters across a package. Qualcomm’s argument is that shortening that trip provides both high bandwidth—the rate at which data moves—and lower energy use.

That differs from the conventional high-bandwidth memory approach Giaretta described. HBM increases the number of lanes and the speed of data transfer between memory and a processor. He argued that this comes with premiums in power, cost and complex packaging. HBC instead places computing directly under the memory, making it more than a replacement memory component.

The handoff to AI250

Those figures describe memory bandwidth and bandwidth per watt, not equivalent multiples of complete-model speed or total system efficiency. Qualcomm’s system-level explanation depends on keeping most decoding work—the calculations that generate a model’s output—inside HBC. The central processor can then instruct that accelerator and receive results rather than repeatedly move the underlying data back and forth.

Giaretta said that arrangement protects end-to-end performance despite the slower AI250-to-LPDDR interface compared with HBC’s internal connection. In his description, HBC acts as a coprocessor: AI250 has substantially more raw calculation capacity, but the near-memory accelerator handles the work that benefits from staying beside the data. The division of labor is central to Qualcomm’s claimed advantage.

Qualcomm plans to integrate HBC into Dragonfly AI250 as a full inference accelerator platform, which will underpin its Dragonfly Rack infrastructure. AI250 sampling is expected in the first half of 2027. Giaretta also cast the lab validation as evidence supporting Qualcomm’s goal of high-yield manufacturing next year—a manufacturing expectation attached to the milestone, rather than an achieved production outcome.