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The Astra SR200 family pairs AI acceleration with more integrated memory. Its power-saving claims still lack independent validation.
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Synaptics’ Astra SR200 family brings Google’s open Coral neural accelerator into three processors for multimodal AI at the edge, paired with Cortex-M cores and expanded memory. The 200–400 GOPS lineup targets devices too constrained for larger application processors; Synaptics pitches shared software and pin-compatible designs as a way to scale products without reworking systems. The chips are still sampling, with no prices or firm volume-production date, and independent tests have not verified the claimed power advantage.
The memory system combines up to 8MB of SRAM with custom DRAM scaling to hundreds of megabytes; Synaptics claims roughly one-third the power of typical system DRAM for comparable workloads.
The SR210 is rated at 200 GOPS, the SR230 at 300 GOPS, and the SR250 at 400 GOPS; peak figures alone do not establish real-world model speed.
Google released the Coral NPU architecture under Apache 2.0 in October 2025; Synaptics is its first commercial silicon partner, but the complete chip is not open source.
Synaptics introduced three AI processors on October 20, 2026, aimed at running voice, vision and sensing models inside small devices rather than in the cloud. The Astra SR200 family uses Google’s open-source Coral design, but the chips are still being sampled, with no disclosed prices or firm timetable for volume production.
Synaptics calls the design an “xMCU,” its label for a microcontroller with expanded computing and memory capabilities. It targets workloads that exceed conventional microcontrollers’ memory limits but cannot accommodate the power and cost of larger application processors. Intended devices include AI wearables, battery-powered sensors, connected cameras, and industrial voice and vision systems.
The memory design pairs up to 8MB of SRAM, a type of on-chip memory, with custom DRAM that can scale to hundreds of megabytes. Synaptics says that capacity lets larger models combine inputs such as voice, images and motion entirely on the device, without needing external memory in most applications.
The company claims its custom memory architecture runs comparable workloads at roughly one-third the power of typical system DRAM. That is a memory-level claim, not a demonstrated threefold improvement in device battery life. Independent benchmarks have not yet established the overall battery-life advantage, VentureBeat notes.
Computing is divided among specialized components. Alongside Coral’s neural processing unit, or AI accelerator, the chips combine Arm Cortex-M85 and Cortex-M52 cores. A high-performance core handles control, multimedia and bursts of computing, while an efficiency core handles always-on sensing, connectivity and low-power AI processing.
Synaptics rates the entry model at 200 billion operations per second, targeting power-efficient, always-on voice and sensing.
The middle model adds vision, display and optional audio capabilities for devices combining several kinds of input.
The top model supports dual vision and display paths for more demanding on-device applications, according to Synaptics.
Google open-sourced the Coral NPU architecture in October 2025 under the Apache 2.0 license. Other chipmakers can incorporate that accelerator design into commercial processors without paying Google licensing fees or royalties. Synaptics is Google’s first commercial silicon partner for Coral, combining the open architecture with its own proprietary processing technology.
The software is intended to reduce the work of adapting models to different chips. Synaptics’ open-source Torq compiler, which translates models for the hardware, uses the MLIR and IREE software projects. It supports frameworks including PyTorch, JAX and Google’s LiteRT rather than requiring developers to start with a proprietary vendor toolchain.
Within the SR200 family, the three product lines share pin-compatible hardware and a common software development kit. Synaptics says that lets manufacturers move between performance levels while preserving their software investment and system architecture.
The new family enters a market with other AI-capable microcontrollers. STMicroelectronics’ STM32N6 offers up to 600 GOPS through a proprietary accelerator. Renesas introduced its RA8P1 family in 2025 with up to 256 GOPS. Those figures place the SR200 range in context, but they do not establish which chip runs a particular model faster.
Memory capacity, power consumption, software compatibility and the model being run can all change real-world results. Synaptics is therefore selling a combination of memory, integrated audio and vision, and open development tools—not simply the highest operations-per-second number.
A forthcoming Coralboard SR development board is planned around the SR250, with support for up to 256MB of memory. It will provide a way to experiment with the new processor, but Synaptics has not yet made that board available.
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